|
Timings |
Pi |
|
|
1M
average |
1M Sigma |
|
|
4-4-4-11 |
14.8262 |
0.057277 |
|
5-4-4-12 |
14.8186 |
0.032408 |
|
4-4-4-12 |
14.8032 |
0.028021 |
|
4-5-4-12 |
14.8064 |
0.021019 |
|
4-4-5-12 |
14.794 |
0.017117 |
|
5-5-5-12 |
14.8186 |
0.008591 |
|
Timings CAS-tRCD-tRP-tRAS |
2M average |
2M Sigma |
|
4-4-4-11 |
37.2565 |
0.088308 |
|
5-4-4-12 |
37.2703 |
0.089413 |
|
4-4-4-12 |
37.3017 |
0.146518 |
|
4-5-4-12 |
37.3468 |
0.079124 |
|
4-4-5-12 |
37.3736 |
0.142463 |
|
5-5-5-12 |
37.4248 |
0.110838 |
CAS
(tCL): CAS stands for Column Address Strobe or Column
Address Select. It controls the amount of time in cycles between sending a
reading command and the time to act on it. From the beginning of the CAS to the
end of the CAS is the latency. The lower the time of these in cycles, the
higher the memory performance.
tRCD: RAS to CAS Delay (Row
Address Strobe/Select to Column Address Strobe/Select). Is the amount of time
in cycles for issuing an active command and the read/write commands.
tRP: Row Precharge Time. This is the minimum time between active
commands and the read/writes of the next bank on the memory module.
tRAS: Min RAS Active Time. The amount of time
between a row being activated by precharge and
deactivated. A row cannot be deactivated until tRAS
has completed. The lower this is, the faster the performance, but if it is set
too low, it can cause data corruption by deactivating the row too soon.